In an article published on November 3 in npj Unconventional Computing, the authors define the concept of modern analog computing. The work titled 'Modern analog computing for solving differential and matrix equations' is led by Sun Chong from the Institute of Artificial Intelligence and School of Integrated Circuits at Peking University. Co-authors include Piergiulio Mannocchi from the Polytechnic University of Milan and Unconventional AI, as well as Manuel Le Gallo and Abu Sebastian from IBM Research Europe in Zurich. This was reported by QbitAI on the same day.
The review highlights three main elements: solving differential equations, solving matrix equations, and performing matrix-vector multiplication. These elements utilize a common set of operators—summers, multipliers, and integrators—and are mathematically linked because discretized differential equations transform into matrix equations that can be solved either by repeated matrix multiplication or in a single step using an analog closed-loop network. The authors trace the implementation from discrete components to resistive memory and CMOS-based integrated circuits, and also discuss applicability, accuracy, scalability, connection to in-memory computing, and computational complexity.
According to Sun, the modern approach differs from analog computers that were superseded by digital chips decades ago in three ways. First, it focuses on matrix loads in artificial intelligence and wireless communications, rather than exclusively on differential equations. Second, it is based on resistive memory devices, such as memristors, instead of CMOS-based analog circuits. Third, it employs engineering methods to achieve high accuracy and scale.
In a crossbar of such devices, one operand is programmed as the device's conductance, while the other is applied as voltage; thus, Ohm's law performs each multiplication, and Kirchhoff's current law sums each column. Consequently, a 1000x1000 array contains a million multipliers, whereas the CMOS-based analog chip from 2016 mentioned by Sun contained only four integrators and eight multipliers. Adding feedback using an operational amplifier allows the circuit to achieve the solution of a matrix equation in nanoseconds.
This review builds upon earlier work by Sun. In 2019, his team demonstrated the single-step solution of a matrix equation on a 3x3 resistive array in the journal PNAS, with an error of about 3%. In the 2025 Nature Electronics paper, bit slicing with eight conductance states per device was used to achieve a fixed accuracy of 24 bits, reducing the relative error to $10^{-4}$ after three iterations, and then to $10^{-7}$, comparable to FP32, and scaled up to 512x512 matrices using a block algorithm. According to the team's estimates, the throughput was approximately 1000 times, and energy efficiency was about 100 times higher than the Nvidia H100 core and digital FP32 ASICs. These metrics have not yet undergone independent verification.
Discussed applications include real-time robot motion control, massive MIMO signal detection for 6G, and second-order optimization for training large models.
