ChangXin Memory Technologies (CXMT) has responded to Micron's assertion that the 4F² DRAM cell layout does not provide a real increase in density. According to a report published by CXMT for investors on October 31, the company's next technological platform, the sixth generation, is based on the 4F² architecture and has already passed engineering sample verification. The first products based on 4F² will reach customers by the end of this year, followed by mass production contingent upon customer validation and market demand.
The main dispute concerned the factors limiting bit density in DRAM. Scott DeBoer, President and Chief Technology and Product Officer at Micron, stated during the company's webinar on October 21 that Micron will continue to develop the 6F² path and focus on 3D DRAM. He noted that the company had studied 4F² for over twenty years but had not found a viable scaling path, calling some aspects of the 4F² discussion a 'smokescreen.' In DeBoer's view, the theoretical limit of density is determined by the size and pitch of the capacitor, not the transistor arrangement method.
CXMT did not dispute the physical principles but described increasing bit density as a complex systemic problem where word lines, bit lines, and capacitor structures compete for space. The company emphasized that for each architecture at a given node, there is a cost curve determined by process integration complexity, the number of lithography steps, and the thermal budget. CXMT stated that the choice between different approaches depends on the memory manufacturer's technological history, existing production line availability, patent portfolio, and cost structure, and such decisions deserve understanding and respect.
According to an analysis from November 1, Samsung and SK hynix are continuing to develop 4F². Samsung presented a 16 Gbit 4F² prototype at ISSCC 2026, which integrates vertical channel transistors with hybrid copper wafer-to-wafer interconnects. The company plans to use 4F² on its 10a, 10b, and 10c nodes before transitioning to 3D DRAM on the 10d node. Samsung Semiconductor CTO, Jong-Hyuk Son, reported on October 12 that work on 4F² is ongoing. SK hynix uses a vertical gate route, which, they claim, increases bit density by more than 20%, and tested read and write operations on test arrays in July, planning to present work on capacitive 4F² at IEDM in December.
CXMT's version utilizes a Vertical Surrounded Gate (VSG) type transistor, according to the analysis. The company claims to have been working on 4F² since its inception and possesses over 300 published patent families related to this technology. Since 4F² increases density by changing the cell layout rather than reducing line width, it reduces the area factor from 6 to 4 within the limits achievable by DUV lithography. CXMT announced that DDR5 RDIMM, combining 4F² with hybrid interconnect, will appear around the end of the year. The analysis warns that server modules have strict reliability requirements, so the first version will primarily serve for technology verification.
