XHEART Company Releases X7 Ultra Chip with 700 TOPS Performance and Plans X9 for 2027
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XHEART Company Releases X7 Ultra Chip with 700 TOPS Performance and Plans X9 for 2027

The automotive chip company XHEART, established as part of the Momenta chip program, unveiled its X7 Ultra chip on October 29. The company positions this chip as a solution specifically designed to work with large control models, estimating its computational power for such tasks at 700 TOPS.

The head of XHEART noted that the development began with the observation that driver assistance software is shifting from numerous small models to a single, comprehensive large model, which requires corresponding chip adaptation. When the company was founded in 2023, the decision was made to work in reverse, starting from the models actually used in vehicles, and organizing computation, memory, and data movement around them, leaving room for future models.

The X7 Ultra is equipped with a very large NPU core. XHEART claims that data transfer within a single core occurs orders of magnitude faster, reaching terabytes per second, compared to data transfer between cores. A multi-level cache, designed for high throughput and parallelism, aims to reduce inference latency and power consumption. A specialized operator engine accelerates key Transformer operations, such as LayerNorm, Softmax, and Transpose, and also supports FP16 and FP32 vector mathematics to maintain model accuracy.

According to the company's data, production models running on the chip meet benchmark results with 99.99 percent accuracy, and compute utilization reaches 98.7 percent. Compared to products the company calls industry flagships, XHEART states an 80 percent reduction in memory bandwidth consumption and a doubling of energy efficiency. These figures are presented by the company itself and have not undergone independent testing.

The chip also includes, according to XHEART, China's first mass-produced automotive Armv9 processor, which demonstrates 20 percent higher performance and 10 percent better energy efficiency. The architecture with a large cluster improves the coordination of multi-core processors and access to L3 memory, while the new SVE2 vector engine provides higher signal processing performance compared to the previous generation NEON.

XHEART also demonstrated its next chip. The X9 model targets 3000 TOPS for large model computations and 700 GB/s memory bandwidth per chip, with its release planned for 2027. It will be developed jointly with next-generation world-class models, synchronizing computation and memory access for efficient operation of larger models.

The company reports being in a cycle of producing one generation, developing the next, and researching a third. Two years have passed from its founding until mass production. The first X7 chip was operational within 24 hours of returning from the factory, and on the 17th day, the chip, low-level software, and control model were working together in a full vehicle.

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Lenovo unveiled preliminary version of AI Host P7 with Houmo M50 and CIX P1 chips and launched early access program
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Lenovo unveiled preliminary version of AI Host P7 with Houmo M50 and CIX P1 chips and launched early access program

Lenovo demonstrated the preliminary model of its AI Host P7 device at the CSDN's 2026 1024 Programmers' Day and AI Builders Conference on October 24. Additionally, an early access program was launched, inviting initial users to test the device in real coding and office tasks before its general release. Previously, the concept of this portable AI host was presented by Lenovo in May, and this preliminary version includes more detailed technical specifications and software features.

The device weighs about 300 grams and is built on two domestic chips. The first is the in-memory computing inference chip Houmo AI M50, which, according to Houmo, provides 160 TOPS performance while consuming 10 watts. The second chip is the agent SoC from CIX Technology P1, manufactured using a 6nm process and equipped with a 12-core Armv9.2 processor and a 30 TOPS NPU, enabling 45 TOPS in heterogeneous computing.

According to CIX, the P1 chip is responsible for system management, task execution, and planning, and it can interact with external accelerators to run a 122-billion parameter model with a 128K context at a speed of 50 tokens per second. Lenovo claims that the preliminary P7 version is capable of locally processing models with up to 125 billion parameters and a 256K context.

The device comes with a local model library that includes Qwen3.8-Flash-Next, Qwen3.8-27B, and Qwen3.6-35B-A3B, as well as models for speech recognition, speech synthesis, document processing, and image design. Lenovo reports that its internal AI computing architecture, which uses mixed INT4 and INT8 quantization, achieves an average of 98.3% of the baseline BF16 with full precision across four benchmarks. It should be noted that these figures are company data and have not undergone independent testing.

Lenovo positions the P7 as a personal token hub. The token manager function allows users to direct coding tools and agent applications to local models via an API address, thereby saving routine model calls on the device instead of using paid cloud quotas. The task execution mode operates around the clock, and progress can be tracked from phones, tablets, and PCs. The built-in Tianxi AI has an Auto mode that distributes requests between local and cloud models depending on their complexity.

Sun Ke, Head of AI Hosts, emphasized that true productivity should not start with counting token costs. Lenovo has not yet disclosed the price or release date, only stating that the P7 will be available soon.

Stars Micro System Unveils PCIe 6.0 Switch, 800G AI Network Card, and RAID Chip
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Stars Micro System Unveils PCIe 6.0 Switch, 800G AI Network Card, and RAID Chip

WuXi Stars Micro System Technologies has introduced three interconnect chips designed for artificial intelligence clusters and servers. The company, founded in 2020, held its first full-stack and brand product launch in Uxi on October 15, demonstrating 12 interconnect chips that are already in mass production alongside new components.

The centerpiece of the presentation was the C82-4G, which the company named the first PCIe 6.0 switch developed in China. It is capable of supporting up to 144 lanes at 64 GT/s per lane, doubling the per-lane speed of PCIe 5.0. The switch utilizes PAM4 signaling and FLIT mode, ensuring non-blocking switching with a latency in the range of 100 nanoseconds, as well as support for fabric networking, CXL memory expansion, and memory pooling. It is designed for internal connections in next-generation AI servers, where switches extend processor PCIe lanes to GPUs, network cards, and solid-state drives.

The second product is an 800G multi-protocol AI network card, which the company positions as the first such development from a Chinese supplier. This card incorporates a PCIe Gen6 switch with 48 lanes, supports 800G line-rate transmission with microsecond-level latency, offloads RoCE v2, and offers programmable congestion control. The company notes that the card is optimized for Hygon processors and next-generation supernode architectures focused on inter-node communication in clusters comprising tens of thousands of accelerators.

The third component presented is a multi-mode RAID chip, created using domestic intelligent capabilities. It supports SAS, SATA, and PCIe 5.0 connections, is compatible with both hard drives and SSDs, features a hardware encryption block, and, according to the company, increases throughput and IOPS by approximately eight times compared to the previous generation.

CEO Guo Erhui emphasized that computing power is a system of tightly coupled components: computation, networking, data storage, power, cooling, and planning. He noted that as clusters grow to tens of thousands of cards, interconnects become the bottleneck. The company reported that its products are already used in the internet, finance, telecommunications, and energy sectors, with stated failure rates for the chips being less than 100 DPPM, and for the boards being less than 500 DPPM.

During the launch, cooperation agreements were signed with Kylin Software, UnionTech, Tencent Cloud, Inspur, H3C, ZTE, and Lenovo. These agreements cover the adaptation of the company's interconnect chips to their operating systems and server platforms. The company stated that future steps include the mass production of the next-generation network card and PCIe 6.0 switch, as well as work on optical interconnects and storage pooling. It should be noted that all stated specifications are company claims and have not undergone independent verification.

Glenfly Unveils GF800, the First Arm SoC Chip with Proprietary Graphics and Dedicated NPU
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Glenfly Unveils GF800, the First Arm SoC Chip with Proprietary Graphics and Dedicated NPU

Glenfly Tech, a Shanghai-based graphics processor developer, has announced the completion of debugging for its first Arm-based system-on-chip, the GF800, which is now being provided to end customers for testing. Company executives demonstrated the chip and corresponding boards at the 26th China International Industry Fair in Shanghai. According to an interview published by Xinhua Finance on October 16, the company positions this product as a transition from simply manufacturing video cards to offering a complete system-level platform.

The GF800 integrates an eight-core processor featuring full-size Arm Cortex-A78 cores with a graphics processor designed by Glenfly itself, a dedicated neural processing unit (NPU), and a unified memory architecture. This unified memory is utilized by the processor, the GPU, the NPU, and the video blocks. An official statement from Glenfly, posted on its website in August, emphasizes that this is the first instance where the company has integrated its proprietary GPU intellectual property into an SoC.

The market for Arm-based SoCs features major GPU options such as Arm Mali, Immortalis, Qualcomm Adreno, Samsung Xclipse, and Imagination PowerVR; the Glenfly design is presented as an additional, independently developed option. The graphics processor supports DirectX 12, OpenGL 4.6, OpenGL ES 3.2, OpenCL 3.0, and Vulkan 1.3 standards, and Glenfly asserts that it has passed all relevant compliance tests. Furthermore, it includes a specialized 2D engine.

The chip is built on the Glenfly HMUA hardware architecture and the Glenfly HUCA software platform, which, according to Glenfly, are designed to handle model migration, deep learning framework essentials, large model inference, and multimodal deployment. For display operations, the GF800 offers HDMI 2.1, DP 1.4, eDP 1.4b, and DSI interfaces, allowing control of up to four independent displays supporting up to 8K output and HDCP content protection. The new image processor accepts inputs up to 48 megapixels. Interfaces include PCIe 4.0, USB 3.2, SATA, eMMC, and Gigabit Ethernet.

In terms of software, the chip is optimized for domestic operating systems such as UOS from UnionTech and Kylin, while also supporting Linux, Android, and being compatible with Windows. The target applications for the GF800 cover AI terminals, edge servers, industrial computing equipment, and robotics. Deputy CEO Wu Wenzhe noted that the goal is not merely to move cloud computing to devices, but to bring computation closer to data, devices, and industrial applications within real power and cost constraints. Strategy Director Wang Yuanfeng stated that the chip is currently undergoing adaptation and verification of solutions in graphics, display, system compatibility, and industry scenarios. Glenfly has not yet disclosed the NPU performance rating, manufacturing process, or mass production timelines.

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