Lenovo unveiled preliminary version of AI Host P7 with Houmo M50 and CIX P1 chips and launched early access program
Read more
Pandaily
pandaily.com

Lenovo unveiled preliminary version of AI Host P7 with Houmo M50 and CIX P1 chips and launched early access program

Lenovo demonstrated the preliminary model of its AI Host P7 device at the CSDN's 2026 1024 Programmers' Day and AI Builders Conference on October 24. Additionally, an early access program was launched, inviting initial users to test the device in real coding and office tasks before its general release. Previously, the concept of this portable AI host was presented by Lenovo in May, and this preliminary version includes more detailed technical specifications and software features.

The device weighs about 300 grams and is built on two domestic chips. The first is the in-memory computing inference chip Houmo AI M50, which, according to Houmo, provides 160 TOPS performance while consuming 10 watts. The second chip is the agent SoC from CIX Technology P1, manufactured using a 6nm process and equipped with a 12-core Armv9.2 processor and a 30 TOPS NPU, enabling 45 TOPS in heterogeneous computing.

According to CIX, the P1 chip is responsible for system management, task execution, and planning, and it can interact with external accelerators to run a 122-billion parameter model with a 128K context at a speed of 50 tokens per second. Lenovo claims that the preliminary P7 version is capable of locally processing models with up to 125 billion parameters and a 256K context.

The device comes with a local model library that includes Qwen3.8-Flash-Next, Qwen3.8-27B, and Qwen3.6-35B-A3B, as well as models for speech recognition, speech synthesis, document processing, and image design. Lenovo reports that its internal AI computing architecture, which uses mixed INT4 and INT8 quantization, achieves an average of 98.3% of the baseline BF16 with full precision across four benchmarks. It should be noted that these figures are company data and have not undergone independent testing.

Lenovo positions the P7 as a personal token hub. The token manager function allows users to direct coding tools and agent applications to local models via an API address, thereby saving routine model calls on the device instead of using paid cloud quotas. The task execution mode operates around the clock, and progress can be tracked from phones, tablets, and PCs. The built-in Tianxi AI has an Auto mode that distributes requests between local and cloud models depending on their complexity.

Sun Ke, Head of AI Hosts, emphasized that true productivity should not start with counting token costs. Lenovo has not yet disclosed the price or release date, only stating that the P7 will be available soon.

Similar stories

Alibaba introduces RISC-V automotive processor IP and roadmap for autonomous driving and robotics
Read more
technode.com

Alibaba introduces RISC-V automotive processor IP and roadmap for autonomous driving and robotics

DAMO Academy from Alibaba unveiled the XuanTie E908A automotive processor IP at the RISC-V summit in Shenzhen, China, on October 19. This processor IP is designed for safety-related systems, domain controllers, and automotive gateways, and complies with automotive functional safety requirements ASIL-B and ASIL-D, according to DAMO Academy.

Furthermore, the company disclosed a processor roadmap intended for autonomous driving and embodied artificial intelligence. The planned automotive processor C950A is expected to deliver five times the performance of current RISC-V products for the automotive industry, with its release anticipated by the end of 2027.

DAMO Academy reported that the cumulative volume of chips utilizing the XuanTie processor IP has exceeded 6 billion units as the company expands its application from established areas into high-performance computing markets.

DAMO Academy Unveils RISC-V XuanTie E908A Automotive Processor Certified to ASIL-B and ASIL-D Standards
Read more
pandaily.com

DAMO Academy Unveils RISC-V XuanTie E908A Automotive Processor Certified to ASIL-B and ASIL-D Standards

Alibaba's DAMO Academy introduced the XuanTie E908A processor design, optimized for automotive applications, at the RISC-V summit in Shenzhen on October 19. The event also unveiled the company's first roadmap concerning autonomous driving and embodied intelligence.

It is important to note that E908A represents an IP core for a central processor, not a finished chip. DAMO provides this development to semiconductor manufacturers, who then integrate it into their automotive systems-on-a-chip. Thus, E908A serves as a building block for future vehicular silicon solutions, rather than a product available for purchase today.

According to DAMO, E908A is the first RISC-V CPU core to simultaneously meet both ASIL-B and ASIL-D functional safety levels. ASIL-D is the most stringent level under the ISO 26262 standard, applied to functions where failure could threaten life, such as braking and steering. Furthermore, DAMO claims that E908A exceeds the Single Point Fault Metric (SPFM) by over 90%, which the company calls an industry debut. SPFM measures the proportion of hardware single-point faults that the design can detect or localize before danger arises.

DAMO plans to use E908A for three types of tasks within the vehicle: safety islands, monitoring cores that oversee the main processor's operation and take over control in case of failure, and domain controllers and onboard gateways responsible for routing traffic between electronic control units. All these components require predictable real-time computations.

Another part of the announcement was the roadmap. DAMO stated that the XuanTie team is developing high-performance automotive processors for robotics, which shares many requirements with the automotive industry, as well as for autonomous driving. The next-generation processor, C950A, is expected to achieve five times the performance compared to existing RISC-V-based automotive products. DAMO did not provide an exact release date or detailed technical specifications for C950A.

C950A is an evolution of the XuanTie C950, a high-performance RISC-V processor that DAMO presented in March. At the summit, DAMO's chief scientist, Meng Jianyi, emphasized that transitioning high-performance RISC-V from being viable to reliable and subsequently mass-produced requires continuous engineering effort and validation.

This step is significant for the RISC-V ecosystem because safety certification in the automotive industry has long been one of the main obstacles to adopting the open instruction set in safety-critical vehicle systems. A certified IP core reduces costs for chip developers wishing to create RISC-V-based automotive components without needing to develop their own safety-qualified CPU.

The specified safety ratings and target metrics for C950A are proprietary statements made by DAMO.

Popular