Lanxin Computing introduces supernode based on its LX500 RISC-V architecture inference chip
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Lanxin Computing introduces supernode based on its LX500 RISC-V architecture inference chip

Lanxin Computing, headquartered in Shenzhen, has released a so-called supernode for convergent computing. This product expands the RISC-V AI inference platform from a single chip and server level to a cluster system.

The product unveiling took place at the RISC-V Summit in China in 2026, where CTO Jia Xinxia delivered the keynote speech on the LX500 processor that underpins this system.

The core design concept aims to minimize data movement. In a standard inference server, the central processor and a separate accelerator card have their own memory, and model weights, activations, and context data are transferred between them via the PCIe bus. Lanxin's approach integrates general-purpose computing and AI computing onto a single die, allowing both to utilize a shared memory pool. The company claims this improves time-to-first-token, pre-processing, and long-context handling metrics.

According to the company, the LX500 is equipped with 48 RISC-V cores, divided into 32 high-performance and 16 energy-efficient cores. It also includes AI vector and matrix engines capable of performing 75 TOPS of INT8 operations. The chip supports precisions from INT4 to FP32, uses shared DDR5 memory, and supports CXL memory expansion. Previous company materials indicated that the chip conforms to the RVA23 profile and RVV 1.0 vector extension.

The supernode completes the product line that Lanxin has been building over the past year. The LX500 processor was launched in February, publicly demonstrated in April, and used in a universal prototype in May. In July, Lenovo's WR5219 G5 server model built on this chip was introduced, and in August, the company began supplying LX500 samples to industrial customers, some of whom have started small-batch testing.

The current product assortment ranges from the chip and server up to the universal LX5000 device and the new supernode. However, Lanxin has not disclosed the number of chips in the supernode or the types of interconnects, leaving the system's scale undefined.

Regarding software, the company reported adapting Qwen, DeepSeek, and Kimi models for various parameter sizes, precisions, and long-context settings. Work is currently underway on a unified hardware and software stack to simplify the deployment process. Target applications include private enterprise knowledge bases with augmented retrieval, office agents, financial compliance analysis, offline question answering in government agencies, and on-site industrial inspection where local processing and data security are critical.

The release of this product adds a system product to the growing collection of Chinese RISC-V developments focused on data centers, alongside recent announcements of server CPUs and core intellectual property from other domestic developers. Whether the approach will be scalable depends on the performance evolution of the chips, the support of the software ecosystem, and real-world adoption.

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Ascend, MetaX, Biren, and Moore Threads Announce Day One Support for StepFun Step 5 Preview

Following StepFun's release of the Step 5 Preview model weights on October 15, several domestic computing platforms responded promptly. Huawei, MetaX, Biren, and Moore Threads announced day one support for this model, meaning it can be loaded and served on their hardware immediately upon release.

Huawei reported that its Ascend platform supports the model using the vLLM Ascend inference engine. The company developed an optimization package based on the model architecture and the Atlas 950 SuperPoD hardware. This work includes fused operators written in Ascend C and Triton, multi-threaded parallelism, reduction of computational bubbles, MTP speculative decoding, and NPU graph execution.

Furthermore, Huawei noted that on October 15, the first liquid-cooled Atlas 950 SuperPoD system was launched with 1024 cards simultaneously with the release of Step 5 Preview. Although the SuperPoD product line was introduced earlier, the news is that the first full-scale 1024-card installation is now operational, utilizing Step 5 Preview as a workload for launch. Huawei claims that this system achieves a performance of 1 EFLOPS at FP8 format and 2 EFLOPS at FP4, features 256 TB of globally unified memory, and has an interconnect latency of up to 3 microseconds, comparable to cutting-edge computing systems elsewhere. These figures are proprietary data from Huawei.

MetaX stated that its C series GPUs completed day one adaptation using its proprietary MXMACA software stack. The company indicated that as of December 2025, it provided such adaptation for 43 flagship models, including models from Zhipu, Alibaba's Qwen, MiniMax, DeepSeek, StepFun, and Tencent Hunyuan.

Biren adapted the model on its general-purpose GPUs using vLLM and its BIRENSUPA software stack. Functionality and accuracy tests were performed, and weight loading, service startup, and text generation were initiated. The company reported that its SUPACODE platform automatically parsed and adapted key model modules, such as DSA, SummaryCache, and MoE layers.

Moore Threads announced that its MTT S5000 training and inference card and MUSA software stack were able to run the model on day one, having undergone configuration at the hardware, software, and inference framework levels.

Day one support from multiple vendors is becoming standard practice during major open-weight model releases in China, providing developers with greater hardware choice for deployment from the start.

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