October 14, 07:24Pandaily

ModelBest releases MiniCPM-V 4.7, the first MoE multimodal model running on a phone using 3GB of memory

ModelBest has introduced a new version of its lineup of multimodal models designed for device operation—MiniCPM-V 4.7. This model is available in two sizes: 35B-A3B and 1B. Notably, the 35B-A3B version is the first model in the MiniCPM-V series to feature a Mixture-of-Experts (MoE) architecture.

The weights, code, and documentation for this model have been published in the OpenBMB repository on GitHub under the Apache-2.0 license.

Efficiency on Mobile Devices

The primary claimed advantage is its high efficiency when running on smartphones. ModelBest asserts that the 35B-A3B model, which activates approximately 3 billion parameters per token, can operate on an iPhone 17 Pro Max using only about 3GB of RAM. Furthermore, its decoding speed exceeds 13 tokens per second.

The company attributes this result to a new inference acceleration technique they call LES (lookahead expert scheduling), characterizing the model as the first open-source MoE model capable of functioning seamlessly and without loss directly on the device.

Testing Results and Comparison

According to the team's presented benchmarks, the 35B-A3B model achieves the following results: 91.72 on MMBench, 91.2 on OCRBench, and 90.21 on CMMLU. In instruction mode, ModelBest claims it surpasses Qwen3.6 35B-A3B in overall score while requiring less reasoning time.

The 1B version has improved baseline capabilities compared to MiniCPM-V 4.6. Additionally, the company reports that this version outperforms Qwen3.5 0.8B in both overall score and inference efficiency.

Testing conducted by QbitAI showed that the model successfully handles graph reasoning tasks and converting academic articles into Markdown format, all while operating offline on a phone, which targets confidential local document processing.

Platform Support and Additional Tools

MiniCPM-V 4.7 supports iOS, Android, and HarmonyOS operating systems. The model has been adapted to work with chipset platforms from Intel, AMD, Arm, Rockchip, and Houmo AI, allowing it to be used on both mobile gadgets and local PCs.

Alongside the model itself, ModelBest has provided the open-source code for the Self-Replay Fine-Tuning (SRFT) method. This fine-tuning method is designed to assist developers in adding new features with minimal overhead while preventing the forgetting of previously acquired skills.

This release continues the steady rollout of models in the MiniCPM line, following MiniCPM-V 4.6 in May and the text model MiniCPM5-2B in September.

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pandaily.comOctober 14, 10:40

MemSilicon introduced the MountTai 2026 RRAM chip with a 1T4R architecture

The Chinese memory startup MemSilicon announced the completion of the tape-out process for its first high-density and high-capacity RRAM chip, named MountTai 2026, which took place on October 12. The company claims this is the world's first RRAM chip of this type featuring high density and large capacity, although this statement has not yet been independently verified. The chip is currently undergoing validation after the tape-out.

The MountTai 2026 chip is designed using a 28nm CMOS process and features a 1T4R cell structure. It provides a capacity of 1 Gbit per chip, achieves a density of 30 Mbit per square millimeter, and has an access latency of less than 20 nanoseconds. Furthermore, the chip incorporates on-chip hardware error correction.

RRAM, or Resistive Random-Access Memory, retains data by changing the material between resistance states and holds it when power is off. In a standard 1T1R configuration, each resistive cell is equipped with its own selector transistor. However, as cell sizes shrink, the area occupied by these transistors and their wiring becomes a limiting factor for density. The 1TnR approach allows one transistor to serve multiple cells, thereby reducing the transistor area per bit; MountTai 2026 uses one transistor for four cells.

Using a shared transistor introduces several issues, including current leakage paths between cells, read and write disturbance, and reliability problems under various operating conditions. MemSilicon states that it has resolved these issues at the circuit level by implementing a negative voltage design and a unified reset scheme to suppress array leakage, multi-voltage wordline drivers that separate high and low voltage read and write paths, adaptive protection polarization to reduce incorrect writes, and an adaptive sensing scheme with tracking that works in conjunction with error correction to improve read yield at gigabit capacity.

The company's technology is based on the work of Liu Min, a fellow of the Chinese Academy of Sciences, who published research on 28nm 1T2R RRAM design in 2020. Since the cells are created in back-end layers compatible with standard CMOS, this method is intended for embedding non-volatile memory into logic chips.

MemSilicon is targeting on-board storage for model weights, KV caches, and parameters in SoCs, edge AI devices, and AI PCs, where SRAM is fast but consumes significant space per bit, and integrating embedded flash memory becomes increasingly difficult as logic processes scale down.