IIT Madras plans to create 1000 startups by 2032 and aims for monthly IPOs

Before the start of the student admission season at IIT, important news emerged: the institute banned cooperation with 22 companies for the next two years. These companies had previously provided students with employment letters but subsequently failed to fulfill their hiring commitments.

These firms will now be excluded from the student recruitment process for the next two campus seasons. This decision was made after these companies either withdrew or failed to honor many job offers for graduates planning to finish their studies in 2026 last academic year, which created problems for the affected students.

In light of this situation, IIT decided to cease cooperation with such companies within the campus recruitment framework. This decision was reached during the active preparation period of IIT institutions for the new admission season.

Considering the difficulties faced by students, this decision was made at a meeting of the All IIT Placement Committee (AIPC) at IIT Guwahati at the beginning of this month. AIPC is the central body that sets guidelines for internships and placements across IIT campuses.

Although the panel recommended using the term 'non-cooperation' instead of 'blacklist,' IIT will use this specific terminology. John Joss, an Associate Professor at IIT Guwahati and AIPC Coordinator, told ET that it concerns over 150 offers from 23 IITs, with some companies withdrawing between 10 and 15 offers. He did not disclose the names of these companies.

However, according to campus sources, Oracle is among the companies under 'non-cooperation' for two years because it allegedly failed to fulfill about 40 offers made to IIT students. This American software company conducted mass layoffs globally this year, including in India. Reports also indicate that various startups are included in the list of companies facing action.

IIT is also taking steps to assist the students whose offers were canceled. Placement offices have circulated the resumes of these students among active recruiters and requested that candidates be considered for available vacancies. It is estimated that about 20–30% of the affected students managed to find jobs this way through mutual contacts.

Nevertheless, IIT does not have complete information on the number of students who are still looking for work. Some graduates may have found jobs independently off-campus or through personal connections without notifying their educational institutions.

Support for microchip design startups in India will receive a significant boost following the Union government's approval of the Semicon 2.0 program, which provides for more than doubling state support for this segment. The Minister of Electronics and Information Technology, Ashwini Vaishnaw, announced this during a fireside chat at the SEMICON India 2026 event on September 18, 2026.

His comments, made as the second phase of India's semiconductor incentives was formulated, place the country's ambitions in the chip domain at the center, encompassing both deep technology developers and SME manufacturing bases, alongside large investments in fabrication plants.

Ashwini Vaishnaw noted that India's pursuit in semiconductors began six years ago under Semicon 1.0. He emphasized that previous attempts, spanning nearly six decades, had repeatedly failed due to inconsistent policies and short-sightedness.

This time, the government has developed a program based on a twenty-year roadmap and a phased approach. This approach started with Assembly, Testing, Marking, and Packaging (ATMP) units and the first fabrication plant for a relatively less complex, high-throughput chip segment—on a node from 28 to 90 nanometers, which, according to the minister, accounts for about 70% of the global chip volume. It is worth noting that Semicon 1.0, planned as a six-year project, was completed in only four years, allowing for the creation of a foundation for its successor.

Semicon 2.0, approved with allocations of ₹1.275 billion, is based on six key areas: design, materials and equipment, additional fabs, expansion of ATMP capacities, research and development, and talent. Vaishnaw pointed out that chip design proved to be the most startup-dense area among these directions.

Under Semicon 1.0, the government eliminated, according to Vaishnaw, the biggest hurdle for young design companies—the high cost of licensing Electronic Design Automation (EDA) tools from suppliers like Cadence, Synopsys, and Siemens. Instead of funding individual licenses, access to these tools was organized jointly through the Centre for Development of Advanced Computing (C-DAC). As a result of this step, over 105 startups became chip designers, with 20 of them attracting venture capital, estimated at around ₹800 billion, according to early government data.

Building on this foundation, Semicon 2.0 aims to support at least 200 companies engaged in deep chip design, which Vaishnaw called a potential turning point for Indian intellectual property.

Beyond chip design, Vaishnaw highlighted the program's positive impact on small and medium Indian manufacturers. Quoting an industry leader he met at the event but not naming the company, he reported that the company had already begun exporting components worth about ₹2,000 billion from India, with almost 90% of this component ecosystem sourced from SMEs.

He added that the precision manufacturing capabilities established around electronics assembly are now being utilized across various sectors, including mobile phone production, aerospace components for companies like Airbus, and defense industries, in addition to semiconductors. One executive Vaishnaw spoke with noted that his company's board of directors informed him there was no actual limit on investment in India, provided execution timelines were met, which he felt indicated investor confidence in the program.

To support this transition, the government is implementing a multi-tiered training system, starting with a Level 1 course lasting 240 hours, designed to prepare a student immediately after high school with skills comparable to a college engineering graduate at subsequent levels. A specialized Institute of Precision Manufacturing is soon planned, followed by similar institutes.

Regarding the total number of specialists, Vaishnaw stated that India has set a goal to train 85,000 semiconductor design engineers over ten years and has already trained about 70,000 in the first four years. He clarified that other recent government statements indicate achieving the full target of 85,000, so the exact current number may vary depending on the date of the last update. Furthermore, he noted that the target of one hundred thousand cleanroom technicians under Semicon 2.0 would likely require an increase given industry demand.

One detail from the conversation helps explain the rapid growth of chip design startups in India. EDA tools are specialized software used for chip layout and modeling before production. Licenses from suppliers such as Cadence and Synopsys can exceed a startup's early-stage annual budget.

Instead of subsidizing individual purchases, the government viewed access to EDA as shared infrastructure through C-DAC, allowing startups to design chips without bearing these costs independently. Vaishnaw suggested that this approach influenced the development of India's chip design ecosystem more than direct grants, as it lowered the barrier to even attempting to design a chip. However, it remains an open question whether this model will hold up when scaled to a cohort nearly double the initial one under Semicon 2.0.

In conclusion, Vaishnaw mentioned that India's first fab, the Tata Electronics-PSMC facility in Dholera, is expected to reach first silicon in 2028. He noted that the spot reserved for this silicon in his office is currently empty, serving as a reminder of how much of the Semicon 2.0 promises still needs to be realized. For chip design startups and SMEs supporting this ecosystem, the upcoming phase will test how well policy based on shared infrastructure and phased training can scale beyond the initial group.

Amitesh Kumar Sinha, Additional Secretary of the Ministry of Electronics and Information Technology and CEO of the Indian Semiconductor Mission, stated that acquiring a government-backed startup is not necessarily a failure but can be a return on investment. This distinction is becoming increasingly significant as India transitions to the next stage of its semiconductor industry development.

According to Tracxn data, Indian semiconductor companies have attracted cumulative equity funding of $1.4 billion, with about half of this amount, $701 million, raised since 2025. Now, the government plans to attract more private capital into chip development through joint investments with venture funds.

Speaking to Shraddha Sharma, founder and CEO of YourStory and The Bharat Project, just before the opening of Semicon India 2026 in New Delhi, Sinha outlined the concept of Semicon 2.0—the second phase of the mission, which transforms the government's role from a mere grant provider to a co-investor. Under this model, the government will co-finance venture capitalists' investments in approved chip startups at a one-to-one ratio on the same terms.

He noted that 'initial funds for startups are grants; the rest is our investment, so the government shares both successes and failures.' When YourStory previously interviewed Sinha before Semicon India 2025, the Indian Semiconductor Mission had 10 approved projects and provided electronic design tools to 280 colleges. A year later, the number increased to 12 manufacturing units with cumulative investment commitments exceeding 1.64 lakh crore rupees: this includes one silicon foundry, one silicon carbide-based factory, one gallium nitride micro-LED display integrated factory, and nine packaging units. Three of these 12, namely Micron, Kaynes, and CG Semi, have started commercial production, and all are located in Sanand, Gujarat.

In the design domain, support was approved for 24 startups, and Sinha reported that 15 of them attracted venture funding. The first phase, which began in 2022 with an allocation of 76,000 crore rupees, is called Semicon 1.0. The Union Cabinet approved Semicon 2.0 on July 15, 2026, with an allocation of 127,500 crore rupees, and MeitY notified the scheme on August 31, 2026. This program is built on six pillars: design, equipment and materials, fabs, advanced packaging, research and development, and talent.

Sinha emphasized that the timely arrival of Semicon 2.0 demonstrates the long-term commitment shown by Prime Minister and Union Minister Ashwini Vaishnaw. According to Sinha, the first phase aimed to establish demand. The 12 approved projects showed the government what it needed in the supply chain and identified gaps. He explained that 'when your industry is still small, supply chain partners prefer to export to India rather than relocate here.' As a result, only basic goods are established near the plant.

Semicon 2.0 aims to bridge this gap. He explained that equipment accounts for about 65% of the cost of a manufacturing facility, while chemicals, gases, and materials account for approximately half of operating expenses. Attracting such suppliers to India reduces production costs and increases the competitiveness of Indian companies.

Sinha also noted that the time is right for India. Since the global semiconductor industry is expected to expand sharply in the coming years, manufacturers and suppliers will have to scale up capacity somewhere. India's bet is that the growing domestic market, government incentives, and forming manufacturing base can convince more suppliers to move here.

However, the most significant change is happening in the design sector. Under the first phase, the scheme provided startups and MSMEs with initial funding and access to automated electronic design tools, which are prohibitively expensive for a small team. The problem arose after concept validation. Sinha clarified that chip design takes another one and a half to two and a half years depending on complexity, and this requires funds not covered by the scheme. The cost of designing a single chip can range from 25 crore to 35 crore rupees for a simpler version to 1,000 crore to 2,000 crore rupees for complex components.

Semicon 2.0 adds a layer of co-investment. After receiving initial funding, if a venture fund invests in an approved startup, the government invests an equal amount as an investor on the same terms. Large Indian companies that may not want to give up a stake can opt for royalty-based financing, which is also co-financed at a one-to-one ratio. Exit routes align with industry practice, and any company can exit when it decides to do so.

The goal is to attract venture funds to a sector they have largely avoided. Sinha stated that 'in Silicon Valley, Israel, wherever design companies thrive, venture funds invest, understand the business, mentor startups, and help with market access.' He is ready to address the political question that arises when a government-backed startup is acquired by a foreign company. 'If we try to control it, the ecosystem will not form,' he said. The founder being acquired returns with capital and experience, tries again, and after one or two attempts, creates a company that the mission truly wants—an Indian fabless firm with its own intellectual property. If the startup is acquired, the government receives its share according to its stake, just like any other investor, and uses this money to fund the next. In other words, Semicon 2.0 is not designed to prevent exits. Its goal is to create a cycle where successful exits return capital and experience to the ecosystem.

Shraddha asked what share of domestic chip demand the domestic capacity can meet and by when. Sinha answered by segments rather than a single date. In packaging, he expects India to cover domestic demand and export in large volumes within five to six years, taking a leading position in advanced packaging. Even then, 10% to 25% of unique, advanced chips will still be imported because their factories are not here.

In fabrication, the Tata plant in Dholera covers nodes from 28 nanometers to 110 nanometers, and he expects full capability above 28 nanometers to follow with the emergence of more compound semiconductor fabs under Semicon 2.0. In the long term, over 10 years, he said India will achieve self-sufficiency in legacy chips and begin exporting them after meeting its own needs. The most advanced chips at the 2nm level and below may continue to be imported. 'This could take 10 to 12 years,' he noted.

Shraddha's concluding question set a 10-year horizon: what must happen by 2035 for him to call the mission game-changing? His criterion was a specific goal: self-sufficiency in legacy fabs and all types of packaging with large export volumes—that is the baseline. If India closes the gap in advanced technology by then, 'I will call it a success.' If it operates parallel to the advanced level, 'I will call it a super success.'

According to PIB, the Indian semiconductor market was valued at $45 billion to $50 billion in 2024-25 and is projected to reach $100 billion to $110 billion by 2030.

Shraddha asked a question that a student from Patna, Indore, Bhubaneswar, Coimbatore, or Kochi might ask: is this industry only for Tata and IIT startups? Sinha began his answer with design, which he said constitutes about 50% of the semiconductor value chain, with 20% of global design engineers already being Indian. The Chips to Startup program provides free expensive design tools to over 300 colleges, according to PIB, and student projects are manufactured in the Semiconductor Laboratory in Mohali, packaged, and sent back. 'A student who sees the full cycle leaves college as a confident design engineer,' he said.

He added that the Design Linked Incentive scheme attracts Indians with 25-30 years of design experience abroad who now want to start businesses at home. A chip design company hires from 50 to 200 people, and if it scales, 'it becomes Qualcomm, which hires 20,000 engineers in India.' Besides design, he listed chemical, materials science, civil, and mechanical engineering as fields upon which the fab depends, mentioning an industry multiplier of about 5.7 for jobs created outside the plant.

The most striking example for him was Shraddha's comment that deep technological discussions often exclude women. At the CG Power plant in Sanand, operators working with semiconductor equipment and packaging chips are all women recruited from Jharkhand, Madhya Pradesh, Bihar, Odisha, and Northeast, with ordinary education and no prior industry experience. They were sent for training to Malaysia, many of them leaving their hometowns for the first time. 'Meet them today, and they will explain chip packaging to you as confident engineers,' he said. He noted that women already constitute more than half of the electronics workforce, and at some plants, the entire workforce, and he expects this to happen in the semiconductor industry too. Semicon India 2026 will hold a special session on women in the industry, where senior Indian women leaders of global chip companies will speak to students.

Semicon India 2026 will take place from September 17 to 19, 2026, at Yashoboomi in Dwarka, New Delhi, opening with Prime Minister Narendra Modi on September 17, and he will hold his annual Country Roundtable with global CEOs on September 16. Sinha reported that more than 575 companies are participating, compared to 350 last year, of which about 300 are international, and 86 are headquartered in India. Participation has grown to over 50 countries and seven national pavilions, and he noted that 12 states are participating. SEMI, which refrained from holding the conference in India in 2022 and 2023 due to lack of industry, has been collaborating with ISM and IESA since 2024.

This year's novelty is the workforce development pavilion within the exhibition, including student mentorship, training on the full fab process, a one-day session conducted by experts from Singapore on September 18, and company-sponsored hackathons. The Semicon India 2026 mobile app offers navigation of the venue, session schedules, and coordinated AI matching with the ability to book meeting rooms. Main sessions will be broadcast for those who cannot travel to Delhi.

By the metric used by the mission, a design startup becomes a unicorn with revenue of $1 billion. 'Many unicorns are what we want to see in semiconductor design,' Sinha said. Alongside export volumes from legacy fabs and packaging units, he wants the mission to be evaluated in 2035 in this way.

A closer test is quieter. He reported that order negotiations with large global companies for fabs that are now starting commercial production are at an advanced stage; some are ready to book entire facilities and are already discussing expansion at yet-to-be-built plants. If these orders come in over the next year, they will provide an early indication of whether the Indian semiconductor surge is moving from government-supported capacity creation to a commercially sustainable industry. And by Semicon India 2027, the mission may be measured against a completely different baseline than the one it sets this September.