Alibaba's chip development division, T-Head, has introduced its latest accelerator for artificial intelligence training and inference—the Zhenwu V900. The presentation took place at the Apsara conference in Hangzhou on September 22, according to an English press release from Alibaba Cloud.
This review focuses specifically on the chip itself—its memory, interconnect, and production timeline—rather than the broader V900 supernode architecture utilizing ICN Switch, smart NICs, and SSD controllers, which were covered separately.
According to company materials, the Zhenwu V900 demonstrates approximately three times the performance of the Zhenwu M890, which was released in May. Furthermore, the new accelerator is equipped with 216 GB of memory and provides an inter-chip bandwidth of 1200 GB/s. The chip natively supports multiple data precisions, including FP8 and FP4, allowing it to be used for both high-precision training and low-precision inference.
T-Head explains that the increased on-die memory capacity helps reduce the overhead associated with model sharding and data movement when handling dense workloads, while the wider inter-chip connection path is necessary when numerous accelerators must function as a single machine.
Mass production and commercial release of the Zhenwu V900 are planned for the first quarter of 2027. TechNode's report within the Apsara presentation adds that the V900 is based on T-Head's proprietary parallel computing architecture and is designed to work with the ICN Switch interconnect. This enables over 1000 cards to share native memory semantics and unified addressing.
Alibaba also stated that the Zhenwu line has served over 650 clients across sectors such as automotive, finance, large language models, embodied intelligence, energy, and manufacturing. These deployment figures are self-reported by the company.
For buyers tracking domestic silicon solutions for AI, the key takeaways are: this is a next-generation Zhenwu accelerator with roughly triple the performance of the M890, featuring 216 GB of memory, 1200 GB/s interconnect, and a Q1 2027 production window. No independent third-party benchmarks were presented at the launch; actual cluster performance will depend on the readiness of the supplied silicon and the software stack.