ChangXin Memory Technologies (CXMT) has announced the start of mass production for its fifth-generation DRAM platform, named the G5 Platform. This significant milestone was presented at the World Manufacturing Conference 2026 in Hefei, where a new line of LPDDR5X developed on this platform was also showcased.
The DRAM manufacturer from Hefei positions G5 as technology that reduces the gap with the most advanced high-volume memory platforms across key manufacturing metrics. Furthermore, G5 offers smartphone and portable device manufacturers a new option for high-density mobile memory for global electronics supply chains.
From a process perspective, CXMT reports an active half-pitch of 11.95 nanometers for memory arrays, achieved using the Self-Aligned Quadruple Patterning (SAQP) method. The company also noted that after redesigning the process technology and integrating new materials, the capacitor aspect ratio reached 45:1, and the height of the main cell array was reduced to 6,762 nm by utilizing an HKMG flow optimized for DRAM.
Supporting developments include a digital twin line covering design, sample release, manufacturing, and yield maintenance, as well as advancements in interface engineering, saddle ridge structures, and low dielectric constant bit lines.
The commercial advantage lies in crystal density. Compared to CXMT's fourth-generation platform, the gross crystal density per wafer on G5 exceeds the previous platform's figures by at least 50% at a base level of 8 Gbit, which was measured before defect testing, confirming claims of better cost and power efficiency competitiveness.
Two LPDDR5X products with a capacity of 24 Gbit per die debuted on the G5 platform: this represents a 50% increase in capacity compared to similar SKUs offered in 496-ball and 245-ball packages for phones and consumer electronics, and they are already in mass production.
Vice President Luo Xiaodong stated that the production capability is now 'comparable to the most advanced mass production nodes' in the industry. As reported by Reuters, the platform is designed to create more powerful memory while reducing costs and power consumption. The main focus of this story is CXMT's achievement with G5 DRAM and 24 Gbit LPDDR5X, differing from previous reports about CXMT's NAND R&D plans or rumors of viable HBM, focusing instead on scaling SAQP, increasing die density, and commercializing mobile memory, rather than speculation about stacked memory.