Huawei introduces Lingqu UnifiedBus as the foundation for the Agentic SuperPoD cluster architecture
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Huawei introduces Lingqu UnifiedBus as the foundation for the Agentic SuperPoD cluster architecture

At the Huawei Connect 2026 event in Shanghai on September 17, Huawei ICT BG CEO Yan Chaobin introduced Lingqu UnifiedBus as the central interconnection element for a new joint cluster and SuperPoD architecture designed for Agentic AI workloads.

Huawei explained that as clusters grow, efficiency often decreases due to card communication latency. Furthermore, training models with 10 trillion parameters and frequent data exchange between agents and models push the KV Cache and intermediate data far beyond the memory of a single card, making the factory design a performance bottleneck.

The core principles of Lingqu's design include protocol unification: over ten interconnect protocols are merged into a single factory with Lingqu memory semantics. Interconnect bandwidth increases from the 100 GB class to the TB class, and round-trip time is reduced from approximately 7 microseconds to 2 microseconds, enabling global memory access within the SuperPoD.

Central Processing Units (CPUs), Neural Processing Units (NPUs), memory, and Solid State Drives (SSDs) are connected as equal elements for decentralized access. A flexible ratio of CPU to NPU is provided, along with hardware acceleration for Attention and FFN splitting for AF-distributed deployment. Multi-level storage pools can handle activations and use DDR as secondary memory for NPUs, while the optical network is positioned as a high-speed, low-latency data transmission channel for elastic scaling and expansion.

Huawei also announced multi-level Lingqu interconnect hardware, covering rack, inter-rack, and cluster levels. Modules within the rack eliminate losses from copper cables and circuitry—Huawei claims that a 4096-card SuperPoD can save about 196 kilometers of copper cable. Inter-rack switches provide 176 ports with 1.6 Tbps bandwidth each, delivering 280 TB of optical bandwidth per chassis at an RTT delay of about 2 microseconds. The Lingqu Xinghe UBG network switches advertise a branching factor of 1024, designed to support the construction of SuperClusters with millions of cards as models grow to tens of trillions of parameters.

At this factory, Huawei described the Agentic SuperPoD cluster, which combines Kunpeng 950, Ascend 960 SuperPoD, OceanStor M900 memory storage, and UBG switches for heterogeneous computing and unified resources. A similar interconnection story extends to devices: the Atlas 650E air-cooled server can directly connect 16 NPUs across two nodes without a switch, functioning as a small SuperPoD for on-site trillion-parameter inference. The emphasis is placed on co-designing the system and interconnects, not just the near-packet optics of the Ascend 960 SuperPoD, and this remains a vendor roadmap statement until independent cluster measurements are available.

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Huawei Unveils Ascend 960 SuperPoD with Near-Packaged Optics at Connect 2026 Conference
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Huawei Unveils Ascend 960 SuperPoD with Near-Packaged Optics at Connect 2026 Conference

At the Huawei Connect 2026 event, held in Shanghai on September 17th, Chairman David Wang introduced the Ascend 960 SuperPoD as the next-generation supernode for artificial intelligence. The development focus is placed on interconnect scalability rather than single-chip performance.

According to the system description, the Ascend 960 SuperPoD is the first model to utilize Near-Packaged Optics (NPO). This technology integrates Huawei's Lingqu UnifiedBus factory with the Hi-ONE optical engine, enabling optical connections to be placed closer to the chip package.

According to First Finance and related reports, one Ascend 960 SuperPoD can connect approximately 4096 cards with a round-trip latency approaching 2 microseconds. Huawei asserts that these metrics allow for large-scale training and inference of models up to 10 trillion parameters.

Furthermore, broader delivery information was disclosed: Ascend SuperPoD systems have already been shipped to over 1000 customers from more than 370 companies, indicating the architecture's transition from demonstration stands to commercial use.

The chip roadmap has been adjusted. Huawei announced that the Ascend 960DT is planned for release in the first quarter of 2027, and the Ascend 960PR in the third quarter. The liquid Atlas 960 SuperPoD is also scheduled for release in the third quarter of 2027, three quarters earlier than the initial public forecast, which pointed to the end of 2027 for the Ascend 960. Wang also stated that Huawei has developed 11 UnifiedBus-based chips for large systems and confirmed the long-term goal of creating a million-card SuperCluster.

The main emphasis is on system engineering: this includes NPO optics, UnifiedBus, cooling systems, and cluster software, which allow multiple Ascend cards to function as a single machine. Reuters reports confirm the dual 2027 launch dates and the figures of over 1000 supernodes and more than 370 customers, but did not name the buyers. This news differs from Huawei's 'Intelligent World 2035' report published recently, as it presents specific information about the SuperPoD interconnect and the revised Atlas 960 schedule for operators who are already evaluating Ascend clusters.

Origin Wukong demonstration showed coherent quantum routing with 98% efficiency
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Origin Wukong demonstration showed coherent quantum routing with 98% efficiency

Researchers working on the third generation of the Origin Wukong superconducting quantum computer in China reported in early September the creation of a coherent quantum routing system designed for bucket-style quantum random-access memory.

On actual hardware in Hefei, one quantum router achieved an information transfer efficiency of about 98%, and a two-layer cascaded network demonstrated an efficiency level of approximately 93%. During random access tests, the average fidelity for a single router was 94.8%, and for the two-layer network—82.4%.

This work, involving Origin Quantum in collaboration with the University of Science and Technology of China and other partners, was published in Physical Review X.

Quantum RAM must provide data routing for addresses that are in a superposition state, rather than sequentially through one bucket at a time. Standard decomposition into digital gates makes the routing process deep and fragile as the number of nodes increases, which enhances decoherence. The team in Hefei instead uses auxiliary energy levels in superconducting devices as temporary intermediate states.

Microwave pulses lift the information to higher levels for directed transmission and then return it to computational states, which is more akin to building an overpass than placing traffic lights at a planar intersection.

Address bits are encoded in non-adjacent three-level states, allowing small control errors to be detected and filtered via post-selection, without the need to add heavy additional error correction qubits.

The experimenters built three independent routers on the Wukong chip and connected them into a two-layer network, thus testing cascaded transmissions rather than an isolated block, as was only possible in simulation.

The researchers emphasize that the 98% figure does not mean commercial QRAM readiness. Scaling up to networks of four or eight layers still faces challenges related to microwave crosstalk, cryogenic stability, and integration cost. However, they highlight the achievement of a systemic function on real hardware: coherent, reversible, addressable routing without infinite gate depth, shifting the focus from qubit count competitions to creating usable memory infrastructure.

If we consider quantum computers as factories, memory and routing act as warehouses and highways. The result from Origin Wukong does not complete the roadmap, but it provides a measurable off-ramp onto the highway for quantum data movement, which previously seemed like a dead end, and it does so on a domestic superconducting platform, not a software mockup.

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