Every user of a phone, laptop, or UPI application in India relies on semiconductors, yet most people have never seen the chips themselves. In connection with the opening of Semicon India 2026 in New Delhi on September 17, 2026, Amitesh Kumar Sinha, Additional Secretary of MeitY and CEO of India Semiconductor Mission, held a discussion with Shraddha Sharma, founder and CEO of YourStory and The Bharat Project. He explained in detail how a semiconductor chip is created using a simple analogy—the chip is like a house.
Sinha compared the chip creation process to building a house: first comes the design, then the construction, and finally, doors and windows are installed to make the object functional. This demonstration is important because it explains the basis for the government allocating funds amounting to 127,500 crore rupees for the second phase of the mission, which was announced on August 31, 2026.
Any element that conducts electricity and interacts with the user logically—from a Google search query to AI servers, defense equipment, and home appliances—functions thanks to chips. Like a multi-story house, a chip is built in layers. If a house is designed using CAD tools, a chip is developed using EDA tools, or Electronic Design Automation. The complexity of such a design is so high that Sinha ranks it among the world's most complex technologies.
The majority of financial investment goes into the design stage. Approximately half the cost of the entire semiconductor chain is attributed to design. The cost of developing a single chip can range from a modest 25 crore to 35 crore rupees, while the most complex components can cost from 1,000 crore to 2,000 crore rupees. This is why startups were given free access to EDA tools in the first phase of the mission, and state co-investment is planned for the second phase after a venture fund supports the design startup.
After the design is completed on computers, it is transferred to the fabrication plant (fab). Engineers at this plant require the design in their own machine language, so the development team works with the foundry's Process Design Kit (PDK), which Sinha describes as the foundry's own set of EDA tools. After agreement and creation of the design file, it is sent for production. Sinha compares the factory to a kitchen: 'Give it a recipe, and it will produce the product.'
Chips are not produced one by one. They are manufactured on a large circular crystal, which Sinha equates to the initial structure of a building: columns, pillars, and walls before final finishing. Wafers come in sizes of 12, 8, 6, and 4 inches. For silicon logic and memory fabs, 12 inches is the standard, whereas for connections based on advanced semiconductors like silicon carbide and gallium nitride, 8 and 6-inch wafers are more commonly used today.
The raw material is the wafer itself. Silicon is purified from quartz sand into an ultra-pure crystal, which is grown as a cylindrical ingot and then sliced into thin discs that arrive at the factory with mirror polishing. Inside the factory, a multi-stage process involving hundreds of steps takes place: layers of material are deposited onto the wafer, patterns are printed on them using light in a process called lithography, and unnecessary material is etched away. This cycle repeats layer by layer over weeks until the circuit is complete.
One can imagine many houses on one plot of land. One crystal contains many identical chips, and the process called dicing separates them. Sinha noted that depending on the chip size, one crystal can yield between 5,000 and 50,000 chips.
Each diced chip, or die, then undergoes packaging, which is equivalent to adding electricity, water, doors, and windows. The die is enclosed in a plastic casing top and bottom, and connectors are routed for electrical connection with neighboring chips or a larger system. Only then does the chip become functional. Chip testing is performed twice: first on the crystal to weed out defective dies before dicing, and again after packaging, before shipment. Finished chips are mounted on a printed circuit board or another substrate, and many chips together form a system. A mobile phone can contain between 200 and 250 chips, each responsible for its function: power, communication, processing, and others.
India's first phase of development reflects this sequence. Of the 12 approved projects, nine belong to ATMP units, which handle assembly, testing, marking, and packaging, covering the final part of the process from dicing to testing. Sinha expects India to become a major exporter in this field within five to six years. Fabs located higher up the chain require more time.
Sinha's second lesson concerns costs. Building a chip fab costs approximately between 500 crore to 80,000 crore or 90,000 crore rupees for a large facility. An advanced fab on 3-nanometer or 2-nanometer nodes, where the node denotes transistor density, costs $15–25 billion, comparable to India's total expenditure on Semicon 2.0 or even exceeding it. Sinha reported that equipment accounts for about 65% of the total fab cost, followed by chemicals, gases, and materials, and then logistics, cleanroom design, and skilled precision engineering workforce. This is why Semicon 2.0 aims to attract suppliers, not just the factories themselves.
He also emphasized that no semiconductor industry in the world has been built without government support. In the United States, it began with defense department-funded research that evolved into Silicon Valley; Japan and Taiwan followed similar paths; and developed nations continue to provide incentives. The strategic rationale for this approach is related to costs. According to Sinha, countries have become more cautious about exports and imports since the pandemic. A country denied access to critical chips, especially computing chips for AI worked on by young developers, sees its progress stall. Although no country controls 100% of its supply, even the United States, India aims to have sufficient capacity so that it cannot be isolated.
Visitors to Semicon India 2026 this week will be able to see all these stages—design, manufacturing, testing, and packaging—on the exhibition floor, allowing most people to get close to observing the construction of a house made of billions of transistors.