Axera has released the M9 series of automotive chips designed for Advanced Driver Assistance Systems (ADAS), manufactured using a 5nm process. The flagship model M97 and the core model M95 are key products in this series.
The peak equivalent artificial intelligence computing power reaches approximately 720 TOPS on the M97 and about 360 TOPS on the M95. Thanks to the unified architecture, perception and planning software can be ported between these two models without requiring a complete code overhaul. The company positions this lineup as the computational foundation for higher levels of automated and assisted driving, including urban autonomous driving systems and single-stage end-to-end stacks, rather than as silicon for consumer electronics.
According to Axera, cumulative shipments of intelligent driving chips exceeded 1.6 million units by August 2026, with the previous M5 series already being used in mass-produced vehicles.
The chips are based on self-developed blocks. The Neural Processing Unit (NPU) features a multi-core, multi-cluster structure that accounts for functional safety requirements. The integrated cache, according to the company, performs more than 30% better than comparable domestic developments, and the internal bandwidth reaches the terabytes per second level. It supports common matrix and vector caches, as well as FP4, INT8, FP8, and BF16 formats, ensuring zero-copy paths between the CPU and NPU.
Accompanying toolsets allow the time to bring algorithms to market to be reduced from months to weeks. The integrated Image Signal Processor (ISP) targets a processing latency of less than 10 milliseconds, supports up to 16 input cameras, and achieves speeds up to 4.5 gigapixels per second on the flagship path, utilizing dual computer vision and human display pipelines from a single sensor data source.
The computer vision accelerator handles image preprocessing, vision operations, LiDAR point cloud support, and multi-sensor hardware synchronization without burdening the CPU or NPU.
Memory bandwidth is around 460 GB/s for the M97 with options of 36/48/64/96 GB, and around 260 GB/s for the M95 with options of 12/18/24 GB. The M97 model is equipped with 16 Cortex-A78AE cores, while the M95 uses 10 cores. Both models comply with the AEC-Q100 standard, feature an ASIL-D locked safety island, and are certified at the chip level to ASIL-B standard.
Dual-chip interconnects with speeds up to 64 GB/s enable redundancy for achieving higher automation goals, or they can be used in configurations with a separate cabin chip. Axera reports that internal tests show a higher system frame rate than major competitors, as well as stronger end-to-end and vision-language-action throughput, and approximately 70% lower ISP path latency.
The supplier emphasizes its role as an open computing platform and states that it will not compete with automakers or Tier-1 suppliers in high-level control algorithms. Founder and Chairman Qiu Xiaoxin described this task as creating a stage upon which partners can perform. Work is currently underway to provide engineering samples and select OEMs according to the company's plans, but independent third-party ADAS benchmarks, beyond Axera's own data, have not been published since the announcement.