The high-performance cluster supernode Matrix from ZTE, designed for the domestic market and built on ZTE's OEX architecture, was included in the list of 'Key Achievements in China's Computing Power' at the China Computing Power Conference in 2026, held in Lanfang, Hebei Province.
People's Posts and Telecommunications News, distributed via East Money, noted ZTE's participation among ten key achievements presented at the main forum between September 11 and 13. This recognition reflects a systemic approach, demonstrating how modules, interconnects, and multi-vendor GPU sub-boards are packaged for scaling AI factories, rather than just individual chip performance.
OEX, which stands for Orthogonal Electrical eXchange, is a backplane-less orthogonal connection that directly links compute and switching sub-boards, eliminating the need for internal high-speed cables. ZTE and its partners claim support for dense configurations of around 128 GPUs per rack, reducing SerDes traces by over 30%, decreasing cable failure points, and utilizing modular sub-boards that can be replaced in minutes instead of hours.
The Matrix design combines OEX electrical switching within the rack with distributed optical switching between racks. The goal is to achieve a network latency of 100 nanoseconds while simultaneously reducing losses in photoelectric conversion and connection power consumption. Dynamic reconfiguration of the topology in the optical medium allows clusters to be configured for different training graphs without rebuilding the physical infrastructure.
A significant commercial advantage cited is adaptation time. Thanks to the standardization of mechanical and electrical interfaces of the sub-boards and support for multiple connection protocols, ZTE asserts that the development cycles for the entire machine and chip can be reduced to approximately three to six months, compared to previous timelines of 18–24 months.
The proposal utilizes multi-vendor GPU sub-boards. Partners working on the OEX plus optical Matrix solution include Lightelligence, Biren, MetaX, Enflame, and Iluvatar. These companies specialize in photonic hardware interconnects and various accelerator lines that cluster operators can combine within a single supernode structure.
The conference coverage also highlights two roadmaps promoting both electrical plus optical and optical plus optical connection paths, while simultaneously reducing the power consumption of optical modules in dense connections.
It is also worth noting that the same Matrix technology and its application received recognition at the World AI Conference SAIL in 2026 alongside these partners, strengthening the status of this recognition as part of broader systemic development rather than a one-off award.
For buyers planning large halls for training and inference, this signals infrastructural changes: open sub-board interfaces, shorter adaptation loops from chip to rack, and 100 nanosecond inter-rack latency point to a shift in competitive focus from individual accelerators to complete supernode systems capable of integrating heterogeneous GPU sub-boards across successive product cycles.