Huawei has integrated its Kirin 9050 Pro chip into commercial devices. This chip is the first flagship System-on-Chip developed based on LogicFolding technology, which is a vertical stacking method associated with Tao's Law—a tau scaling framework presented by semiconductor industry leader He Tingbo.
The main focus in developing this product was on the architecture, packaging, and thermal design. It analyzed how active logic folds between layers, how dense vertical connections reduce latency, and how heat is managed when two active dies are stacked.
The first device to use this silicon was the foldable Mate XT 2 trifold, but this is not the central theme of this material. According to Tao's Law, the optimization goal shifts from simply reducing the feature's lateral size to reducing the characteristic tau latency in transistors, circuits, chips, and systems.
LogicFolding technology allows critical digital paths, memory, and selected analog blocks to be distributed across two active layers connected with a pitch of approximately 1.5 microns. This adds millions of vertical interconnections, which Huawei compares to a much denser elevator cage structure compared to traditional 2.5D packaging or simple module-on-module.
According to the company, transistor density reaches about 238 million per square millimeter, higher than the previous 155 million, demonstrating an increase of nearly 55%. Meanwhile, the routing area of the high-speed on-chip network is reduced by approximately 55%, and the SRAM operating frequency is increased by more than 40%.
Key aspects for the commercial offering are power consumption and heat dissipation metrics. With comparable performance to the previous planar version, Huawei reports a 66% reduction in NPU power consumption, 58% in GPU, and 41% in core-performance processor in key scenarios. The overall power density is slightly lower, and the operating temperature is described as lower compared to the preceding model.
Thermal zoning and selective folding prevent hot blocks from being placed directly on top of each other, which is a practical limitation when the bottom die is further from the heat sink. Peak cores are rated for a frequency of 3.1 GHz; thanks to Lingxi CPU hyperthreading, Huawei claims a single-core performance increase of over 24% and a multi-core performance increase of over 52%. Furthermore, hardware ray tracing has been implemented on the Maliang GPU and support for large Mixture-of-Experts models on the Da Vinci NPU within HarmonyOS 7 and Ark Engine.
Although independent laboratories have not yet published full teardown power consumption curves, the density and efficiency figures remain data provided by the manufacturer itself. Previous publications concerning Tao's Law and LogicFolding described theory; this release marks the transition to commercialization—the release of an SoC whose value will be determined by interconnection latency, packaging yield, and sustained thermal dissipation performance as this architecture spreads beyond the first foldable carrier into a wider range of flagship devices.