ChangXin Memory Technologies (CXMT) has reportedly begun producing HBM3E samples, moving high-speed memory modules into an early qualification stage in collaboration with domestic artificial intelligence accelerator developers.
According to industry reports citing The Information, Alibaba's chip division, specifically T-Head and Cambricon, are among the parties evaluating these modules alongside their processors for launching data centers and accelerators.
The sample production is situated between engineering samples and mass production: stacks are leaving the line for customer verification, but yield rates, monthly wafer starts, and final part numbers may still change as thermal and packaging parameters are tuned.
CXMT has not yet published detailed technical specifications for the pilot silicon HBM3E, and this product is absent from the company's public DDR and LPDDR catalog. Therefore, industry analysts consider the capacity, stack height, and supported bandwidth of the future commercial version to be undefined, and neither CXMT nor the named customers have issued a joint public confirmation of the qualification schedule.
The JEDEC HBM3E standard itself is well known: it is a 1024-bit interface, with a data transfer rate of up to approximately 9.6 GT/s per contact and stacks of 8 or 12, which can reach around 24GB or 36GB when using 24GB dies, with a bandwidth approaching approximately 1.2 TB/s depending on the speed grade.
It remains undisclosed whether the CXMT sample batches meet these grades or utilize finer intermediate configurations until the yield from through-silicon vias and soldering quality matures. HBM production also depends on fine interconnects, stacking yield, temperature control, and packaging tests—stages that significantly exceed the capabilities of ordinary DRAM dies and often determine the schedule risk for new first-generation participants.
If qualification with T-Head, Cambricon, and other accelerator developer teams proceeds on schedule, commentators point to the possibility of commercial use as early as 2027, which is often presented as an optimistic timeline rather than a firm volume commitment. This path differs from CXMT's separate story of mass production of mobile LPDDR6 DRAM: HBM3E is focused on AI accelerator memory bandwidth, not smartphone package DRAM, and these two products should not be conflated when planning supply.
In the short term, this news should be viewed as a milestone in the supply chain and product—the entry of domestic HBM3E into the qualification cycles of chip manufacturers, rather than a statement that volume, yield, or full JEDEC class performance is already secured. Telemetry from early customers will determine whether pilot lines turn into stable corporate supply within the next year. Until then, CXMT's HBM3E should be tracked as a qualification-stage product with incomplete public specifications, rather than as a direct replacement for mature, high-volume HBM SKUs already supplied elsewhere.