Automated chip design using artificial intelligence has become one of the most discussed topics in the industry. Last month, the Chinese company Kimi demonstrated a complete experiment where its K3 model independently designed a chip. This chip was tested on an EDA platform, running for 48 hours exclusively on AI, without using commercial software from Cadence or Synopsys.
However, a deeper analysis shows that replacing existing systems is still far from complete: the chip from Kimi corresponds to technologies from about 20 years ago, runs 20–30 times slower than modern chips, and open-source EDA tools still require commercial systems to perform real projects.
Nevertheless, agentic AI is truly transforming workflows, covering tasks from generating RTL code to creating test environments and invoking simulation, formal verification, and debugging tools.
At the DAC Chips to Systems 2026 conference, three leading EDA companies presented their different strategies. Synopsys, possessing the largest accumulation of AI, introduced a fully autonomous agent for design verification and an autonomous thermal simulation workflow based on Ansys Icepak. Furthermore, the company showcased an analog/mixed-signal workflow with a 3x efficiency increase and 20 GPU-accelerated tools. Synopsys proposed an AI autonomy ladder in the style of self-driving transport, from L1 to L5, which is currently at level L3, and launched AgentEngineer in 2026 after DSO.ai in 2020. In November 2025, NVIDIA invested two billion dollars in Synopsys, and Grace Blackwell is expected to provide 30 times higher performance for EDA workloads.
Cadence's strategy focuses on architectural completeness. The company introduced AuraStack—an AI-based superagent that joins ChipStack, InnoStack, and ViraStack to ensure coverage for verification, digital implementation, analog design, as well as printed circuit boards and packaging. This stack provides 20 times higher multiphysics analysis performance and a 15x workflow acceleration. NVIDIA engineers are already using this system. Cadence's most distinctive innovation is the Mental Model—a structured representation of knowledge that fixes design intentions to reduce hallucination risk, and its agents have been recognized by NVIDIA, Qualcomm, and Broadcom.
Siemens EDA adheres to a different approach—trusted autonomy. The core logic of their Fuse EDA AI agent uses self-checking, matching the results of large models with deterministic, physics-based assertion engines. The Solido Layout Analyzer tool helped the STMicroelectronics non-volatile memory team reduce debugging time by weeks, and through Intelligence Center X, Siemens is expanding agent planning to production processes and supply chains. Fuse uses the MCP protocol to connect tools from different vendors. All three giants rely on NVIDIA inference level, management level, and the Vera processor in EDA verification farms.
Chinese manufacturers view the current situation as a favorable moment. Xpeedic, together with Lenovo, presented its EDA agent as the only example of domestic EDA at DAC 2026. XEPIC launched the basic Agentic EDA XEPIC Intelligent System with intelligent verification and design, focusing on proof cycles that transform AI outputs into verifiable, traceable results ready for approval. UniVista released UDA 2.0—the first agentic EDA tool on a fully proprietary domestic architecture. Other solutions include Chips Z for advanced packaging, DVcrew and PDcrew agents from Banxin, and an LLM-based verification platform from Zhiwei Chuangxin called ChatDV, which reduces modular verification from months to hours. NVIDIA research shows that chip designers spend about 60% of their time on debugging—precisely the area targeted by agentic AI.
