Samsung announced, during the Future of Memory and Storage 2026 conference held this Wednesday (5th), a new generation of 3D memories specifically developed for the field of artificial intelligence. This new architecture, named zHBM, promises to significantly accelerate data processing and set a historical feat by stacking over 400 layers of storage cells on a single chip.
Traditionally, in AI systems, memory modules were positioned adjacent to processors. The innovation presented by the company changes this geographical configuration by integrating the memory vertically directly onto the processing chips.
This physical proximity results in much more efficient data transmission. According to the company itself, this provides a file transfer speed up to eight times faster, in addition to increasing energy efficiency threefold.
Training large language models (LLMs) demands the processing of billions of parameters. The main obstacle in these servers is not just the raw processing capacity of the CPU or GPU, but rather how quickly the memory can supply the necessary information. Slow memory forces the processor to wait for the data to arrive before proceeding with its tasks.
By increasing the transfer rate, Samsung mitigates part of this bottleneck. This novelty meets the needs of giants like OpenAI, Microsoft, and Google, allowing their data centers to operate faster and, consequently, with lower operational costs at a large scale.
This launch also strengthens the manufacturer's position as a key supplier for the competitive AI ecosystem. In the last quarter alone, the division responsible for manufacturing memory chips registered a 56% growth in sales.
In addition to server solutions, the company introduced LPDDR5X-PIM memory, being the first in the sector to incorporate Processing-in-Memory (PIM) technology. This functionality allows the memory chip itself to execute data calculations, eliminating the need for a constant flow of information with the device's processor and generating energy savings, which is crucial for mobile devices.
Another technological advance displayed at the event was the new V10 BV-NAND memory standard, focused on storage, which demonstrated a 58% increase in density. The company managed to stack over 400 layers of cells on a single component.
Despite the promising potential of these records, the greatest application of this technology will be in the AI market. Currently, Samsung and its competitor SK Hynix dominate global memory production and are already operating near the limits of industrial capacity. Due to the priority of producing lucrative AI chips, the manufacturing of conventional memories has been relegated to second place.
The shortage of basic components on assembly lines triggers a cascading effect. With lower availability of memory in stock, production costs increase. The final impact falls on the consumer, resulting in higher prices for electronics such as cell phones, laptops, and consoles.
Samsung Electronics announced a new line of memory technologies aimed at artificial intelligence systems on Tuesday (04) during the Future of Memory and Storage conference. The event was held in Santa Clara, California.
The South Korean company showcased the V10 Bonding V-NAND prototype, also known as BV-NAND. This solution was developed to increase storage capacity and enhance the performance of AI applications that require large volumes of data.
The new architecture presented by the manufacturer integrates over 400 layers and uses a wafer interconnection technology that allows for increased memory density, reduced thermal constraints, and optimized power consumption.
With the growing evolution of artificial intelligence systems, particularly those focused on generating user responses, the need for high-capacity memories has significantly increased. In this context, Samsung seeks to consolidate its position in the semiconductor market through the development of specific solutions for heavier workloads.
According to the company itself, the BV-NAND technology represents a progress compared to the previous generation, V9 NAND, showing an approximate 58% increase in memory density. Furthermore, improvements were reported in read, write, and data input/output operations, aspects crucial for applications that rely on ultra-fast storage.
In addition to the new prototype, Samsung demonstrated concepts of architectures named zHBM and zNAND-O, which are part of the corporate strategy for developing three-dimensional memories. This proposal involves the vertical stacking of memory cells to concentrate more information in a smaller space.
The manufacturer explained that the zHBM technology differs from conventional high-bandwidth memories by positioning memory components vertically above artificial intelligence accelerators. This results in a reduction of the data path and an increase in energy efficiency.
Samsung also stated that its wafer bonding technique could enable a memory density more than ten times that achieved by traditional HBM5-based solutions. The company added that this methodology has the potential to triple energy efficiency and reduce thermal resistance by more than half.
This announcement comes amid discussions about the future of memory chip demand. While some investors express concern about the possible effects of a decline in smartphone consumption in China, industry analysts indicate that the advancement of artificial intelligence sustains demand at high levels.
The company recently revealed that long-term contracts with customers can account for between 60% and 70% of its future memory sales. Citi reports also point out that DRAM and NAND supply chain inventories remain below historical averages, even amidst uncertainties in other market segments.
