Huawei has presented measured data for the Kirin 2026 chip as part of the Tao Law V2 publication. According to this data, the chip demonstrates a density of 238 million transistors per square millimeter, achieved through the LogicFolding architecture. This result represents a 53.5% improvement in density compared to the baseline Kirin 9030 Pro model, which has a density of 155 million transistors per square millimeter.
The Kirin 2026 chip was manufactured on the same technological node as the baseline Kirin 9030 Pro model. In addition to increased density, the device demonstrated a 41% reduction in power consumption in normalized mode, an increase in CPU frequency from 2.74 GHz to 3.1 GHz, and an improvement in SRAM operating frequency by over 40%.
Parallel to the release of the Tao Law V2 data, Goldman Sachs adjusted capital allocation towards semiconductor supply chains. Analyst Brian Garrett from Goldman Sachs released a report noting that investors are underestimating American tech mega-caps, preferring positions in the semiconductor sector. Goldman significantly raised price forecasts for memory chips, expecting DRAM prices to grow by up to 280% and NAND flash memory prices by up to 250% by 2026.
Omdia forecasts a global growth in semiconductor revenue of 62.7% year-over-year in 2026, with this growth being driven by the memory sector. TrendForce expects contract prices for DRAM in the third quarter of 2026 to increase by 13–18% quarter-over-quarter.
Chinese companies listed on the local market confirm this market cycle through their financial reports. A memory module market leader reported net profit for the first half of 2026 of 9.2–11.0 billion yuan, representing an increase of 622–744 times compared to the same period last year. Significant income derived from inventory revaluation amid rising memory prices created the strongest profitability cycle in industry history. Profit growth extends across the entire supply chain, including design, manufacturing, packaging, testing, and equipment components.
The CSI Chip Industry Index reflects this opportunity across the entire chain. Unlike narrowly specialized indices, this index, comprising 50 components, covers the entire chip production cycle, accounting for demand for advanced packaging driven by LogicFolding technology, rising memory prices, and equipment localization simultaneously. The ETF tracking this index showed a return of 299.84% over the past two years. The convergence of three factors—confirmed Tao Law technology, institutional capital rotation, and proven revenue growth—enhances the investment potential of the semiconductor cycle.
A joint research group from Peking University and the Shanghai Institute of Microsystems, Chinese Academy of Sciences, has developed the world's first millisecond-level neuromorphic dynamic chip based on phase-change memristors. This development was published in the journal Science on July 14th.
This chip, measuring only 0.28 square millimeters, is capable of achieving a computation latency of 2.12 milliseconds. It integrates in-memory computing arrays for matrix operations and stepped shift arrays for adaptive integration.
The chip fundamentally changes the approach to computation in neural dynamics systems. The traditional Von Neumann architecture separates memory and processor, forcing data to constantly move between them, creating bottlenecks in latency and power consumption when solving differential equations required for neural dynamics. The Peking University team solved this problem differently by using the physical properties of the phase-change memory devices themselves to perform computations, instead of creating faster digital circuits.
Phase-change memristors possess continuously variable conductance, which can be precisely programmed and predictably evolve over time. Researchers mapped the search for adaptive integration required by neural dynamics solvers directly to the evolution of the conductance of these memristors. This means that the search, evaluation, and adjustment of step size—which digital circuits perform through many clock cycles—occurs via physical evolution within the device itself.
Furthermore, multi-level control of conductance allows for the creation of high-density in-memory computing arrays that simultaneously store neural network weights and perform matrix operations within a single array.
Experimental data demonstrates impressive performance. Compared to the most advanced ASIC accelerators, the system provides an acceleration ranging from 3.82 to 36.27 times while reducing power consumption by 3.9–7.8%. In tasks involving high-precision reconstruction of the brain cortex surface, the system outperforms the NVIDIA A100 GPU by 50.38–478.18 times. This marks the first instance where neural dynamics hardware has been brought to millisecond-level real-time operation, enabling applications previously limited to offline processing to become online real-time capabilities.
The article published in Science also contains a review paper describing this work as a paradigm shift in physically controlled computing. The significance of this development extends beyond demonstrated brain modeling and includes potential for real-time brain-computer interfaces, digital brain twins, neural navigation for surgery, and intelligent diagnosis of neurodegenerative diseases. The chip, operating at a frequency of 50 MHz with 9-stage pipelining, shows that architectural innovations can provide orders of magnitude improvement compared to a 'brute force' approach using GPUs for specialized computational tasks.
The research was supported by the New Cornerstone Investigator program, the National R&D Program, and the National Natural Science Foundation, as well as the Guangdong Key Laboratory of In-Memory Computing Chips. This chip represents a distinctly Chinese contribution to the developing field of physically controlled in-memory computing, where performance enhancement is driven by device physics rather than Moore's Law scaling.
Huawei has released the second version of its scientific paper 'Tao's Law,' titled 'A Time Scaling Theory for Multi-Layer Electronic Systems.' This document demonstrates the company's systematic approach to maintaining chip performance scaling in the post-Moore era, despite limitations related to the embargo on advanced EUV and DUV lithography equipment.
The concept of Tao's Law is named after Huawei semiconductor business president He Tingbo. It is based on a complex time constant function $\tau = f(\tau_{transistor}, \tau_{circuit}, \tau_{chip}, \tau_{system})$, which divides system time into four interconnected sub-constants at the transistor, circuit, chip, and system levels. Engineers achieve full scaling of the $\tau$-function by compressing delays at each of these levels.
The Kirin 2026 chip, which will be used in Huawei's flagship smartphones of 2026, is the first mass-produced mobile SoC to confirm the applicability of Tao's Law. Its key innovation is the 'Logic Folding' design methodology. This method distributes registers and logic circuits across two layers (wafers) connected by vertical hybrid bonding interconnects. Unlike vertical stacking of DRAM in HBM, Logic Folding separates functional logic components across multiple die layers to optimize hierarchical layout.
This method can be compared to converting a single-story house into a two-story duplex without changing building materials. By not relying on more advanced lithography or smaller transistor sizes, Logic Folding reduces long metal traces on the chip to short vertical channels between layers. At the circuit level ($\tau_{circuit}$), this ensures the miniaturization of the time constant.
When compared to the baseline Kirin 9030 Pro model, manufactured using identical processes, Kirin 2026, equipped with Logic Folding, achieves a transistor density of 238 MTr/mm² according to Huawei's measurement methodology, which is equivalent to 175.39 MTr/mm² by industry standard (excluding auxiliary isolation and filling devices). This represents a one-cycle density improvement that would traditionally require three years of geometric scaling. This density slightly exceeds the logical density range of the 5 nm planar process from TSMC, which is 138.2–171.3 MTr/mm².
Furthermore, Kirin 2026 reduces the supply voltage by 0.2V while maintaining performance equivalent to Kirin 9030 Pro. The measured power consumption is only 59% of the baseline level, and the power density is 94.4%. Huawei emphasizes that Kirin 2026 uses a conservative implementation of Logic Folding, indicating significant potential for further density increases. The company forecasts achieving a transistor density of 400 MTr/mm² (or 294.8 MTr/mm² by industry standard) or higher by 2035, with Logic Folding enabling Kirin core frequencies to exceed 4 GHz.
Tao's Law is also applicable to artificial intelligence applications in data centers, where over 80% of energy is consumed by data transmission and over 70% of system cost is attributed to data storage. Huawei's implementation for data centers includes a Unified Bus architecture, a Hi-ONE near-package optical engine, and a 3D Folding packaging topology to compress communication time constants at the $\tau_{system}$ level.
