According to several industry sources, the Huawei Mate 90 series is set to launch in September and will feature the HarmonyOS 7 operating system, along with a new Kirin chip developed using LogicFolding technology based on Tao's Law. This move positions the series for direct competition with the flagship Apple iPhone 18 Pro in Fall 2026.
The new Kirin chip utilizes LogicFolding dual-layer stacking technology, which is based on the Tao's Law framework. This technology was presented by a Huawei board member and semiconductor president He Tingbo in May 2026. Compared to the base model Kirin 9030 Pro 2025, the 2026 chip demonstrates a significant leap in transistor density: from 155 million Tr/mm² to 238 million Tr/mm², representing an improvement of 53.5%. This achievement is not due to a reduction in the technological node but rather to LogicFolding, which separates digital, analog, and memory circuits onto two vertically stacked dies using an ultra-thin hybrid connection.
HarmonyOS 7 introduces the philosophy of spatial aesthetics. When moving application icons and cards on the desktop, the system animation provides feedback that mimics a three-dimensional physical world. Furthermore, wallpapers gain spatial depth effects for richer visual layering. The internally updated Ark Engine features a larger performance model that intelligently accelerates specific applications based on user context and geographical information, while background process management prioritizes application retention for smoother multitasking.
The Mate 90 series represents the most comprehensive integration of Huawei's proprietary technologies to date. It combines the Tao Law chip architecture, optimized through system-wide latency reduction instead of traditional transistor scaling, with a deeply adapted operating system. This is the first smartphone to implement the principles of tau-scaling design, covering both transistor-level switching and system-level user experience optimization. Industry observers expect the Mate 90 to set new standards in mobile AI processing, camera system performance, and energy efficiency, leveraging the advantages of the Kirin chip's neural processor and HarmonyOS's distributed computing capabilities. The September launch will pit Huawei's integrated hardware and software ecosystem against Apple's latest flagship, promising one of the most competitive premium smartphone battles in recent years.
Huawei has released the second version of its scientific paper 'Tao's Law,' titled 'A Time Scaling Theory for Multi-Layer Electronic Systems.' This document demonstrates the company's systematic approach to maintaining chip performance scaling in the post-Moore era, despite limitations related to the embargo on advanced EUV and DUV lithography equipment.
The concept of Tao's Law is named after Huawei semiconductor business president He Tingbo. It is based on a complex time constant function $\tau = f(\tau_{transistor}, \tau_{circuit}, \tau_{chip}, \tau_{system})$, which divides system time into four interconnected sub-constants at the transistor, circuit, chip, and system levels. Engineers achieve full scaling of the $\tau$-function by compressing delays at each of these levels.
The Kirin 2026 chip, which will be used in Huawei's flagship smartphones of 2026, is the first mass-produced mobile SoC to confirm the applicability of Tao's Law. Its key innovation is the 'Logic Folding' design methodology. This method distributes registers and logic circuits across two layers (wafers) connected by vertical hybrid bonding interconnects. Unlike vertical stacking of DRAM in HBM, Logic Folding separates functional logic components across multiple die layers to optimize hierarchical layout.
This method can be compared to converting a single-story house into a two-story duplex without changing building materials. By not relying on more advanced lithography or smaller transistor sizes, Logic Folding reduces long metal traces on the chip to short vertical channels between layers. At the circuit level ($\tau_{circuit}$), this ensures the miniaturization of the time constant.
When compared to the baseline Kirin 9030 Pro model, manufactured using identical processes, Kirin 2026, equipped with Logic Folding, achieves a transistor density of 238 MTr/mm² according to Huawei's measurement methodology, which is equivalent to 175.39 MTr/mm² by industry standard (excluding auxiliary isolation and filling devices). This represents a one-cycle density improvement that would traditionally require three years of geometric scaling. This density slightly exceeds the logical density range of the 5 nm planar process from TSMC, which is 138.2–171.3 MTr/mm².
Furthermore, Kirin 2026 reduces the supply voltage by 0.2V while maintaining performance equivalent to Kirin 9030 Pro. The measured power consumption is only 59% of the baseline level, and the power density is 94.4%. Huawei emphasizes that Kirin 2026 uses a conservative implementation of Logic Folding, indicating significant potential for further density increases. The company forecasts achieving a transistor density of 400 MTr/mm² (or 294.8 MTr/mm² by industry standard) or higher by 2035, with Logic Folding enabling Kirin core frequencies to exceed 4 GHz.
Tao's Law is also applicable to artificial intelligence applications in data centers, where over 80% of energy is consumed by data transmission and over 70% of system cost is attributed to data storage. Huawei's implementation for data centers includes a Unified Bus architecture, a Hi-ONE near-package optical engine, and a 3D Folding packaging topology to compress communication time constants at the $\tau_{system}$ level.
He Tingbo, a member of the Huawei board and president of the semiconductor business, published the second version of the Tao's Law article, which details the LogicFolding architecture. This technology allows for a significant increase in transistor density in Kirin chips and paves the way for achieving clock speeds above 4 GHz.
According to Guancha.cn, the article, titled 'Time Scaling Theory for Multi-Layer Electronic Systems,' was posted on the Chinese Academy of Sciences preprint platform ChinaXiv on July 3rd. Compared to the baseline Kirin 9030 Pro 2025 chip, the Kirin 2026 chip utilizing LogicFolding demonstrated an increase in transistor density from 155 million transistors per mm² to 238 million transistors per mm², representing a 53.5% gain. This progress would previously have required three years of geometric scaling.
LogicFolding is a methodology that separates digital, analog, and memory circuits into vertically stacked active layers. This ensures a substantial increase in density without relying on advanced process nodes. He Tingbo presented a development plan for the next decade, forecasting a transition from localized folding of critical paths to comprehensive multi-layer folding, where each package will include three, four, or more active layers.
This evolutionary process is supported by low-temperature hybrid bonding, which alleviates thermal budget limitations between layers, as well as relocating through-silicon via landing points from upper metal layers down to M6, freeing up over 30% of the upper layer routing resources. By 2035, transistor density is expected to reach 400 million transistors per mm² and beyond.
LogicFolding directly addresses the fundamental problem of semiconductor scaling after Moore's Law. The article argues that the traditional metric of geometric scaling has reached its limit, as the development budgets for the 2nm node exceed $1 billion per chip, and transistor costs are no longer decreasing. Tao's Law proposes replacing geometric scaling with time scaling, using a single characteristic time constant tau as a unified optimization goal across twelve orders of magnitude—from transistor switching speeds in picoseconds to data center response times in seconds.
Two examples of validation in production conditions were presented. On a mobile SoC, LogicFolding provided a 55% step increase in transistor density at a fixed process node while simultaneously reducing power consumption by 41% at equivalent performance. For artificial intelligence systems, it is anticipated that the jointly developed unified bus architecture with near-package optical I/O and edge-to-surface 3D stacking will lead to an increase in hardware integration by over 100 times by 2035.
He Tingbo acknowledged that serious difficulties remain, including the development of tooling and methodologies, wafer-to-wafer process variations, and overhead associated with vertical interconnects. The article emphasizes that no single organization can solve these problems alone, positioning the work as an industry report and an invitation for broader industry participation. Furthermore, the research is based on lessons learned from 381 mass-produced chips between May 2020 and May 2026.
Huawei has officially released its openPangu-2.0-Flash model with a total of 92 billion parameters, marking a significant milestone in the company's artificial intelligence ecosystem strategy.
The model was previously unveiled this month at the HDC 2026 conference and became available on open-source platforms on June 30th. The code and weights were posted on GitCode in the Ascend tribe repository.
The openPangu-2.0 series is offered in two versions to accommodate different deployment scenarios. The now-available Flash version has 92 billion total parameters, with 6 billion activated, and is optimized for efficient inference on Ascend hardware. The planned July Pro version features 505 billion total parameters and 18 billion activated parameters, designed for maximum performance in large-scale deployments.
Both models support a context window of 512K tokens, allowing them to process voluminous documents and complex codebases in a single pass.
According to Huawei, the openPangu brand reflects the company's initiative to develop open-source AI models built on training and inference technologies specific to Ascend. The goal is to provide examples of best practice implementations for the Ascend ecosystem, enable next-generation AI agents, and accelerate commercial innovation in artificial intelligence. This forms a positive cycle where improved open-source models stimulate greater use of Ascend, which in turn funds further model development.
The open-source release includes the model weights, basic inference code, and training operators for the Flash version. Huawei committed to releasing seven core components in total, starting from June 30th and continuing through the second half of 2026. Additional components include pre-training code, post-training code, and training operators, all intended to assist developers in working with the Ascend hardware platform and reducing reliance on CUDA ecosystem tools.
Richard Yu, Executive Chairman of Terminal BG at Huawei, formally presented openPangu 2.0 at HDC 2026 earlier this month. This release strategy demonstrates Huawei's commitment to building an open ecosystem around its Ascend AI computing platform, positioning it as a viable alternative to NVIDIA's CUDA ecosystem for Chinese developers working with domestic hardware infrastructure. This move holds strategic importance amid ongoing US export restrictions that limit China's access to advanced semiconductors and AI development tools.
