Huawei has released the second version of its scientific paper 'Tao's Law,' titled 'A Time Scaling Theory for Multi-Layer Electronic Systems.' This document demonstrates the company's systematic approach to maintaining chip performance scaling in the post-Moore era, despite limitations related to the embargo on advanced EUV and DUV lithography equipment.
The concept of Tao's Law is named after Huawei semiconductor business president He Tingbo. It is based on a complex time constant function $\tau = f(\tau_{transistor}, \tau_{circuit}, \tau_{chip}, \tau_{system})$, which divides system time into four interconnected sub-constants at the transistor, circuit, chip, and system levels. Engineers achieve full scaling of the $\tau$-function by compressing delays at each of these levels.
The Kirin 2026 chip, which will be used in Huawei's flagship smartphones of 2026, is the first mass-produced mobile SoC to confirm the applicability of Tao's Law. Its key innovation is the 'Logic Folding' design methodology. This method distributes registers and logic circuits across two layers (wafers) connected by vertical hybrid bonding interconnects. Unlike vertical stacking of DRAM in HBM, Logic Folding separates functional logic components across multiple die layers to optimize hierarchical layout.
This method can be compared to converting a single-story house into a two-story duplex without changing building materials. By not relying on more advanced lithography or smaller transistor sizes, Logic Folding reduces long metal traces on the chip to short vertical channels between layers. At the circuit level ($\tau_{circuit}$), this ensures the miniaturization of the time constant.
When compared to the baseline Kirin 9030 Pro model, manufactured using identical processes, Kirin 2026, equipped with Logic Folding, achieves a transistor density of 238 MTr/mm² according to Huawei's measurement methodology, which is equivalent to 175.39 MTr/mm² by industry standard (excluding auxiliary isolation and filling devices). This represents a one-cycle density improvement that would traditionally require three years of geometric scaling. This density slightly exceeds the logical density range of the 5 nm planar process from TSMC, which is 138.2–171.3 MTr/mm².
Furthermore, Kirin 2026 reduces the supply voltage by 0.2V while maintaining performance equivalent to Kirin 9030 Pro. The measured power consumption is only 59% of the baseline level, and the power density is 94.4%. Huawei emphasizes that Kirin 2026 uses a conservative implementation of Logic Folding, indicating significant potential for further density increases. The company forecasts achieving a transistor density of 400 MTr/mm² (or 294.8 MTr/mm² by industry standard) or higher by 2035, with Logic Folding enabling Kirin core frequencies to exceed 4 GHz.
Tao's Law is also applicable to artificial intelligence applications in data centers, where over 80% of energy is consumed by data transmission and over 70% of system cost is attributed to data storage. Huawei's implementation for data centers includes a Unified Bus architecture, a Hi-ONE near-package optical engine, and a 3D Folding packaging topology to compress communication time constants at the $\tau_{system}$ level.
AIFU Semiconductor, based in Guangzhou, is increasing its production of BAW filter chips to one billion units. This allows it to enter a market previously controlled by Broadcom and Qorvo in the 5G radio frequency filter segment, utilizing patented aluminum nitride single-crystal technology.
AIFU Semiconductor is the only company in China and the third globally to master the complete production chain for BAW filter chips for medium and high-frequency 5G bands. The company aims to achieve an annual production capacity exceeding one billion chips, with a stable yield rate of 98–99%. The company's products are already integrated into the production lines of major terminal manufacturers such as Samsung and ZTE.
BAW chips serve as key elements in the radio frequency front-end systems for 5G and higher networks, directly influencing signal reception quality and the ability of smart terminals to resist interference. Previously, American firms Broadcom and Qorvo effectively monopolized the markets and patents for 5G filters. AIFU Semiconductor managed to overcome this barrier by developing its own technology based on aluminum nitride single crystal (ScAlN), bypassing patent restrictions related to polycrystalline aluminum nitride established by foreign giants.
Unlike the polycrystalline aluminum nitride used in the industry, aluminum nitride single crystal provides superior piezoelectric characteristics and acoustic wave transmission efficiency, making it an ideal material for high-performance BAW filters. The company built the world's first 8-inch mass production line for BAW chips in Guangzhou. In 2015, AIFU Semiconductor launched a pilot 5G SABAR BAW line with a monthly capacity of 500,000 units. By 2020, it expanded production to 30 million units per month. Today, the company maintains stable mass production of nearly 100 chip models.
Thanks to systematic technological breakthroughs in materials, simplification of chip manufacturing processes, and domestic raw material supply, the company has achieved a 30–40% reduction in overall production costs compared to foreign counterparts. Meanwhile, SABAR chips demonstrate an improvement in key performance indicators of more than 20%. One smartphone typically requires over 30 filters covering various frequency ranges, and AIFU Semiconductor's products now support frequencies above 10 GHz. The company has upgraded about 12 sets of semiconductor equipment to support its patented process, with some core components developed in-house. The company's 50 mu (3.3 hectares) headquarters in Guangzhou has completed construction and is undergoing cleanroom equipping.
In addition to mobile communications, AIFU Semiconductor's high-frequency filters are used in satellite internet, Internet of Things (IoT), and automotive communication. The company sees robotics as the next frontier for growth, as robots transition from pre-programmed control to autonomous environmental perception, which requires intensive interaction with wireless signals. Furthermore, the company plans to bring its SAMES sensors to the industrial inspection and automotive electronics markets, aiming to double revenue this year.
He Tingbo, a member of the Huawei board and president of the semiconductor business, published the second version of the Tao's Law article, which details the LogicFolding architecture. This technology allows for a significant increase in transistor density in Kirin chips and paves the way for achieving clock speeds above 4 GHz.
According to Guancha.cn, the article, titled 'Time Scaling Theory for Multi-Layer Electronic Systems,' was posted on the Chinese Academy of Sciences preprint platform ChinaXiv on July 3rd. Compared to the baseline Kirin 9030 Pro 2025 chip, the Kirin 2026 chip utilizing LogicFolding demonstrated an increase in transistor density from 155 million transistors per mm² to 238 million transistors per mm², representing a 53.5% gain. This progress would previously have required three years of geometric scaling.
LogicFolding is a methodology that separates digital, analog, and memory circuits into vertically stacked active layers. This ensures a substantial increase in density without relying on advanced process nodes. He Tingbo presented a development plan for the next decade, forecasting a transition from localized folding of critical paths to comprehensive multi-layer folding, where each package will include three, four, or more active layers.
This evolutionary process is supported by low-temperature hybrid bonding, which alleviates thermal budget limitations between layers, as well as relocating through-silicon via landing points from upper metal layers down to M6, freeing up over 30% of the upper layer routing resources. By 2035, transistor density is expected to reach 400 million transistors per mm² and beyond.
LogicFolding directly addresses the fundamental problem of semiconductor scaling after Moore's Law. The article argues that the traditional metric of geometric scaling has reached its limit, as the development budgets for the 2nm node exceed $1 billion per chip, and transistor costs are no longer decreasing. Tao's Law proposes replacing geometric scaling with time scaling, using a single characteristic time constant tau as a unified optimization goal across twelve orders of magnitude—from transistor switching speeds in picoseconds to data center response times in seconds.
Two examples of validation in production conditions were presented. On a mobile SoC, LogicFolding provided a 55% step increase in transistor density at a fixed process node while simultaneously reducing power consumption by 41% at equivalent performance. For artificial intelligence systems, it is anticipated that the jointly developed unified bus architecture with near-package optical I/O and edge-to-surface 3D stacking will lead to an increase in hardware integration by over 100 times by 2035.
He Tingbo acknowledged that serious difficulties remain, including the development of tooling and methodologies, wafer-to-wafer process variations, and overhead associated with vertical interconnects. The article emphasizes that no single organization can solve these problems alone, positioning the work as an industry report and an invitation for broader industry participation. Furthermore, the research is based on lessons learned from 381 mass-produced chips between May 2020 and May 2026.
